1. Field of the Invention
This invention relates to semiconductor memory systems and particularly to peripheral logic support circuits for providing true and complement logic signals in response to externally applied information signals.
2. Description of the Prior Art
An interface or buffer circuit is required in many electronic systems using semiconductor integrated circuits for charging the voltage levels of logical "ones" and "zeros" developed by one logic system connected to its input to the voltage levels required by another logic system connected to its output. For example, in the application of semiconductor memory systems for use in computers and other products it has become preferable to utilize field-effect transistor (FET) memory systems coupled to bipolar transistor logic systems.
In the past it was possible to design both FET and bipolar circuits in which logic levels were directly compatible without the need for voltage level buffering. In early FET memory systems, all required information and clocking signals were generated by external bipolar circuitry and applied directly to an FET memory array chip. Improvements in FET processing enabled FET storage density to increase to the point that input/output connections to an FET memory chip became to numerous to utilize effectively. Reduction in the memory of input/output connections was achieved by providing peripheral logic circuits located on the memory chips to generate those necessary signals which were easily derived from a minimum of externally provided information signals. For example, although the decoding of memory addresses requires both true and complement signals, a single input can be inverted on the memory chip to provide the complement. Prior art techniques included the use of the bipolar true signal directly and used a logical inverter to generate the complement, see for example, the article, "MOSFET Low-Power Inverter", by J. C. Hsieh et al, IBM Technical Disclosure Bulletin, Feb. 1971, page 2660. Additional techniques included the use of cascaded inverters having their outputs coupled to separate driver circuits, such as shown in U.S. Pat. No. 3,796,893 to Hoffman et al.
Additional advancement in the state of the art produced highly efficient FET and bipolar circuit technologies which used incompatible voltage levels for their logical signals. It became necessary not only to provide all of the logical signals to the memory array but also to translate generally lower bipolar logic signal levels to the relatively higher FET logic signal levels. Although translating from negative bipolar signals to positive FET signals could be achieved by interconnecting power supply terminals, problems still remain. One common problem was that, although sufficient logical "one", or up levels, could be provided by bipolar circuits, in many cases the logical "zero", or low level, was often insufficiently low to completely turn off an input FET. Prior art techniques for insuring FET circuit response under such conditions include the use of ratioed inverters, such as described in U.S. Pat. No. 3,594,736 to Hoffman and U.S. Pat. No. 3,898,477 to Buchanan. Such solutions are undesirable as they require the use of large amounts of DC power and unnecessarily increase the input capacitance which the bipolar signal must drive. The use of an input circuit including a common gate FET amplifier, such as described in the article, "FET Input Circuit", by T. L. Palfi, IBM Technical Disclosure Bulletin, June 1971, page 240 or in U.S. Pat. No. 3,076,700 to Buchanan, can reduce input capacitance.
Additional techniques useful to render bipolar signals compatible with FET input requirements include the use of a source bias potential to effectively increase FET threshold voltage, see U.S. Pat. No. 3,678,293 to Popper or U.S. Pat. No. b 3,848,237 to Geilhufe et al. The use of unstable or unbalanced cross-coupled latch circuits has been proposed in U.S. Pat. Nos. 3,778,784 to Karp et al, 3,795,898 to Mehta et al, and 3,902,082 to Proebsting et al. In such input buffers a cross-coupled latch circuit is initially set in a stable state such that the state will be reversed only in the event that a high level bipolar signal is applied to one side of the latch.
Still further variations may be found in U.S. Pat. No. 3,787,736 to Chin, which describes a circuit in which a high level bipolar signal and a power supply potential are simultaneously gated to a pair of cross-coupled FET ratioed inverters having their outputs coupled to true and complement driver circuits.
Various combinations and modifications of the above prior art techniques have been previously suggested in an effort to increase circuit performance. For example, capacitive voltage boosting techniques, such as taught by U.S. Pat. No. 3,480,796 to Polkinghorn et al, have been implemented in address buffer output drivers. See, for example, U.S. Pat. No. 3,906,463 to Yu.
Although the prior art has provided solutions to many problems found in the past, continued improvement of both bipolar and FET circuitry has created additional problems for which prior art techniques are not ideally suited. For example, many buffer circuits must be specifically designed for a particular type of input signal, such that the FET memory chip has no compatibility with respect to other logic systems. Some circuits are preferable for logic systems in which the high level input is too low, others are preferable where the low level input is not low enough to provide full FET logic level output signals.